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Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs

Created by
  • Haebom

Author

Federico Nicolas Peccia, Frederik Haxel, Oliver Bringmann

Outline

This paper proposes a workflow based on the TVM compiler to efficiently map AI workloads to RISC-V vector units. Instead of relying on existing handcrafted libraries or compiler-specific automatic vectorization, we integrate the RVV extension into TVM's MetaSchedule framework to optimize the performance of diverse AI workloads. Experiments on various RISC-V SoCs on FPGAs and commercial RISC-V SoCs demonstrate an average 46% improvement in execution latency compared to GCC's automatic vectorization feature, a 29% improvement compared to muRISCV-NN, and an average 35% faster mapping than LLVM. Furthermore, the generated binaries exhibit a reduced code memory footprint, making them suitable for embedded devices. The proposed workflow is open-sourced so that it can be applied to other RISC-V extensions.

Takeaways, Limitations

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Takeaways:
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We present a method to effectively utilize the RISC-V RVV extensions using TVM and MetaSchedule.
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Experimentally demonstrating GCC's automatic vectorization and performance improvement over muRISCV-NN.
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Performance improvements also confirmed on commercial RISC-V SoCs.
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Suitable for embedded systems due to reduced code memory space of generated binaries.
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Presenting the possibility of continuous development through open source disclosure.
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Limitations:
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Because these results are evaluations of specific RISC-V SoCs and AI workloads, generalizability may be limited.
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Extensibility to other RISC-V extensions requires further study.
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The complexity of the MetaSchedule framework can make it difficult to use and understand.
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