Daily Arxiv

This is a page that curates AI-related papers published worldwide.
All content here is summarized using Google Gemini and operated on a non-profit basis.
Copyright for each paper belongs to the authors and their institutions; please make sure to credit the source when sharing.

VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilog

Created by
  • Haebom

Author

Xiang Long, Yingjie Xia, Xiyuan Chen, Li Kuang

Outline

This paper proposes VerilogLAVD, a novel LLM-based approach that effectively leverages the structural characteristics of Verilog code for early detection of hardware vulnerabilities. VerilogLAVD introduces the Verilog Property Graph (VeriPG), which provides a unified representation of Verilog code, combining AST-based syntactic information with semantic information derived from control flow and data dependency graphs. LLM is used to generate VeriPG-based detection rules from CWE descriptions, and these rules are used to explore VeriPG to identify potential vulnerabilities. Experimental results on 77 Verilog designs (including 12 CWE types) show that VerilogLAVD achieves an F1-score of 0.54, outperforming LLM-only and external knowledge-based LLM techniques by 0.31 and 0.27, respectively.

Takeaways, Limitations

•
Takeaways:
◦
A New Approach to Verilog Vulnerability Detection Using LLM
◦
Proposing an effective Verilog code representation method using Verilog Property Graph (VeriPG).
◦
Verifying the possibility of generating automated detection rules from CWE descriptions
◦
Performance improvement over existing LLM-based approaches
•
Limitations:
◦
An F1 score of 0.54 is not perfect yet. There is room for improvement.
◦
The size and diversity of the dataset used may be limited. Evaluation using a more diverse and larger dataset is needed.
◦
Performance for certain CWE types may be relatively lower than for others. Performance analysis and improvement are needed for each CWE type.
👍
Made with Slashpage