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PGR-DRC: Pre-Global Routing DRC Violation Prediction Using Unsupervised Learning

Created by
  • Haebom

Author

Riadul Islam, Dhandeep Challagundla

Outline

This paper emphasizes the necessity of leveraging AI-based EDA tools, high-performance computing, and parallel algorithms for next-generation microprocessor innovation. Existing machine learning-based DRC violation prediction has limitations in that it relies on supervised learning methods that require large, balanced datasets and long learning times. In this study, we present the first unsupervised learning-based DRC violation prediction methodology. We build a model using only a single-class imbalanced dataset and set a threshold to determine whether new data is classified or not. The experimental results implemented using 28nm CMOS technology and Synopsys EDA tools show that the proposed methodology achieves 99.95% prediction accuracy and is much faster (26.3x faster than SVM and up to 6003x faster than NN) than SVM and NN models (85.44% and 98.74%, respectively).

Takeaways, Limitations

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Takeaways:
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High accuracy (99.95%) and groundbreaking learning speed improvement (26.3 times compared to SVM, up to 6003 times compared to NN) through the introduction of a DRC violation prediction methodology based on unsupervised learning.
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Reduces the burden of data collection by leveraging unbalanced datasets.
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Contributing to improving efficiency and productivity in next-generation microprocessor design.
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Limitations:
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Further validation of the generalization performance of the proposed methodology is needed. Experimental results for various process nodes and designs are required.
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Due to the nature of unsupervised learning, the interpretability of the model may be limited. There may be a lack of clear explanation of the basis for violation predictions.
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Lack of detailed description of the size and characteristics of the dataset used in the experiment. Performance evaluation on other datasets is required.
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