In this paper, we propose SV-LLM, a large-scale language model (LLM)-based multi-agent system to address the automation, scalability, comprehensiveness, and adaptability challenges of system-on-chip (SoC) security verification. SV-LLM streamlines the SoC security verification workflow by integrating specialized agents for verification question answering, security asset identification, threat modeling, test plan and property generation, vulnerability detection, and simulation-based bug verification. Each agent leverages different learning paradigms, such as network learning, fine-tuning, and search-augmented generation (RAG), to help identify and mitigate risks early in the design phase. We demonstrate the feasibility and effectiveness of SV-LLM through case studies and experiments.
