In this paper, we propose Flora, a three-stage linear floorplanner considering feedthrough and placement to solve the floorplanning problem, which plays a crucial role in optimizing the power, performance, and area (PPA) metrics of a chip. In the first stage, Flora performs coarse-grained optimization of HPWL and feedthrough using wiremask and position mask techniques. In the second stage, it fine-optimizes feedthrough and improves component placement by locally resizing module shapes under fixed boundary constraints. In the last stage, it efficiently places macro and standard cells within each module using a fast tree search-based method, and adjusts module boundaries based on the placement results to enable inter-stage optimization. Experimental results show that Flora reduces HPWL by 6%, FTpin by 5.16%, and FTmod by 29.15% on average, and improves component placement performance by 14% compared to the state-of-the-art floorplanning techniques.
