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SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design

Created by
  • Haebom

Author

Zeng Wang, Minghao Shao, Rupesh Karn, Likhitha Mankali, Jitendra Bhandari, Ramesh Karri, Ozgur Sinanoglu, Muhammad Shafique, Johann Knechtel

Outline

This paper addresses data security issues in hardware design automation using Large-Scale Language Models (LLMs), particularly in Verilog code generation. Verilog code generation using LLMs can pose serious data security risks, including Verilog evaluation data corruption, intellectual property (IP) design leaks, and the risk of generating malicious Verilog code. In response, this paper presents SALAD, a comprehensive evaluation method that mitigates these threats using machine unlearning techniques. SALAD selectively removes contaminated benchmarks, sensitive IP and design artifacts, and malicious code patterns from pre-trained LLMs without retraining. Through a detailed case study, this paper demonstrates how machine unlearning techniques effectively mitigate data security risks in LLM-based hardware designs.

Takeaways, Limitations

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Takeaways:
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We present a novel method for effectively mitigating data security risks in LLM-based hardware design automation by leveraging machine learning.
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Demonstrates the feasibility of a technique to remove sensitive information from LLM without retraining.
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Provides important Takeaways for enhancing the security of LLM-based hardware design automation.
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Limitations:
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Further experiments and analysis are needed to determine the effectiveness and performance of SALAD.
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Verification of SALAD's generalization performance against various types of malware and attacks is needed.
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Further research is needed on the potential information leaks that may occur during machine learning.
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