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Hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation

Created by
  • Haebom

Author

Charles Hong, Brendan Roberts, Huijae An, Alex Um, Advay Ratan, Yakun Sophia Shao

Outline

This paper presents hdl2v, a novel dataset for improving the performance of large-scale language models (LLMs) for Verilog code generation. hdl2v aims to augment the amount of publicly available Verilog data by translating three hardware description languages, VHDL, Chisel, and PyMTL3, to Verilog. We demonstrate that the hdl2v dataset improves the VerilogEvalV2 performance of a 32 billion-parameter open-weight model by up to 23% (pass@10), and that a data augmentation-based fine-tuning approach also improves the performance by up to 63%. We also analyze and present the characteristics of the HDL-to-Verilog dataset for future work.

Takeaways, Limitations

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Takeaways:
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The hdl2v dataset, generated by converting VHDL, Chisel, and PyMTL3 to Verilog, demonstrates that LLM-based Verilog code generation can significantly improve performance.
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Performance improvements in LLM can be achieved without data augmentation or knowledge distillation from large models.
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The hdl2v dataset is also effective in increasing the efficiency of data augmentation-based fine-tuning approaches.
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We provide feature analysis of the HDL-to-Verilog dataset for future research.
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Limitations:
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Further research may be needed on the size and diversity of the hdl2v dataset.
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It is possible that the dataset is biased towards specific hardware description languages, which may result in poor generalization performance of LLM.
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Experimental results for actual hardware implementation and verification are not presented.
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