This paper proposes SecFSM, a novel method that leverages a large-scale language model (LLM) to automate the Verilog code generation of finite state machines (FSMs), which play a crucial role in implementing the control logic of systems-on-chips (SoCs). While existing LLM-based Verilog code generation suffers from security vulnerabilities, SecFSM leverages a Security-Oriented Knowledge Graph (FSKG) to guide the LLM to generate more secure Verilog code. Based on the FSKG, vulnerabilities are identified through user requirement analysis, and security knowledge is then leveraged to generate security prompts that are then provided to the LLM. SecFSM is evaluated on academic datasets, artificial datasets, and proprietary datasets collected from academic papers and industrial cases. The results show that SecFSM outperforms existing methods, achieving a high success rate of passing 21 out of 25 security test cases.
