Maintaining architectural flexibility while achieving high performance, energy efficiency, and cost-effectiveness in the development and deployment of edge AI devices is a critical challenge. This paper presents a chiplet-based RISC-V SoC architecture that addresses these limitations through AI-accelerated modularity and intelligent system-level optimizations. The proposed architecture integrates four innovations onto a 30 mm x 30 mm silicon interposer: adaptive inter-chiplet DVFS, a streaming flow control unit, and an AI-aware UCIe protocol extension featuring compression-aware forwarding; distributed cryptographic security across heterogeneous chiplets; and intelligent sensor-based load migration. Experimental results demonstrate that our proposed architecture achieves ~14.7% latency reduction, 17.3% throughput improvement, and 16.2% power reduction compared to existing chiplet implementations on standard benchmarks such as MobileNetV2 and ResNet-50, while achieving an efficiency of ~3.5 mJ per MobileNetV2 inference (860 mW/244 images/s).
