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VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilog

Created by
  • Haebom

Author

Xiang Long, Yingjie Xia, Xiyuan Chen, Li Kuang

Outline

This paper proposes VerilogLAVD, a novel method for early detection of hardware vulnerabilities. To overcome the limitations of existing methods requiring expert knowledge, this paper presents an approach that utilizes a large-scale language model (LLM) to detect vulnerabilities in Verilog code. The Verilog Property Graph (VeriPG), which represents Verilog code in an integrated manner, combines syntactic and semantic information. Using the LLM, VeriPG-based detection rules are generated from Common Weakness Enumeration (CWE) descriptions. These rules are then used by a rule executor that searches VeriPG for potential vulnerabilities. Experimental results on 77 Verilog designs demonstrate an F1-score of 0.54 for 12 CWE types, demonstrating F1-score improvements of 0.31 and 0.27, respectively, compared to the LLM alone or an external knowledge base.

Takeaways, Limitations

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Takeaways:
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A Novel Approach to Verilog Vulnerability Detection Using LLM
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Effective representation and analysis of Verilog code using VeriPG
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Automated detection rule creation using CWE descriptions
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Performance improvement over existing LLM-based methods
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Limitations:
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Accuracy is not high yet with an F1-score of 0.54
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Evaluation on limited CWE types and datasets
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Additional verification is needed for practical application.
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